The present invention relates generally to a programmable system design, and, more particularly, to patching for program codes in a Read-Only-Memory (ROM).
Many programmable systems employ core processors, such as digital signal processors (DSPs), which can execute instructions stored in embedded program memories. The embedded program memory can be implemented as a random access memory (RAM), a ROM or combination of RAM and ROM. The program data stored in ROM cannot be modified after initial programming.
Patching gives a programmer an option to “overwrite” part of the code in the ROM, and replace them with different instructions in order to fix bugs or enhance a particular feature. Patching is often implemented by redirecting the normal flow of the code to a patch code.
A prior art approach presented in U.S. Pat. No. 6,891,765 by the same inventor has limitations. In that approach, when there is a need to patch a part of program codes, the user assigns a “match address” to the new program codes. When that match address is put on an address bus, a patch logic supplies a branch opcode (e.g., 0x4180 in TeakLite DSP). It is assumed that the processor reads a consecutive address (i.e., “match address+1”) in the following cycle, and therefore, the patch logic always supplies the patch address in the following cycle. But sometimes, although the processor may output the consecutive address on the address bus, it needs another cycle to process internal data, and the processor may read the patch address from the data-in bus not in the following cycle but in one of the later cycles. In this case, the processor may read wrong data and undesirable behavior may happen. The patch address should only be supplied in the cycle when the processor reads the data-in bus.
As such, what is desired is a patching logic that redirects normal program flow to a patching program code in all cases and in any execution flow.